Prepare for ISRO ICRB examinations with verified solutions covering Algorithms, Theory of Computation, Compiler Design, Computer Architecture, OS, Discrete Mathematics, and Computer Networks.
Marking scheme: +3.00 positive, -0.75 negative (ICRB Standard).
Using larger block size in a fixed block size file system leads to
Which of the following statements about synchronous and asynchronous I/O is NOT true?
Consider three CPU-intensive processes, which require 10,20 and 30 time units and arrive at times 0,2, and 6, respectively. How many context switches are needed if the operating system implements a shortest remaining time first scheduling algorithm? Do not count the context switches at time zero and at the end
The performance of Round Robin algorithm depends heavily on
Consider a system having "n" resources of same type. These resources are shared by 3 processes A, B, C. These have peak demands of 3, 4 and 6 respectively. For what value of "n" deadlock won't occur
Consider a set of 5 processes whose arrival time, CPU time needed and the priority are given below
| Process | Arrival Time (in ms) | CPU Time Needed (in ms) | Priority |
|---|---|---|---|
| P1 | 0 | 10 | 5 |
| P2 | 2 | 5 | 2 |
| P3 | 5 | 3 | 1 |
| P4 | 5 | 20 | 4 |
| P5 | 10 | 2 | 3 |
The range of integers that can be represented by an n-bit 2's complement number system is
The switching expression corresponding to $f(A,B,C,D)=\Sigma(1,4,5,9,11,12)$ is
Consider the following boolean function of four variables
$f(w,x,y,z)=\Sigma(1,3,4,6,9,11,12,14)$, The function is
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register?
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interrupts $I_{1}$, $l_{2}$ and $l_{3}$ require the following execution time after the interrupt is recognized:
(i) $I_{1}$ requires 25 micro seconds
(ii) $I_{2}$ requires 35 microseconds
(iii) $I_{3}$ requires 20 microseconds
$I_{1}$ has the highest priority and $I_{3}$ has the lowest. What is the possible range of time for $I_{3}$ to be executed assuming that it may or may not occur simultaneously with other interrupts?
The process of organizing the memory into two banks to allow 8- and 16-bit data operation is called
Suppose the numbers 7, 5, 1, 8, 3, 6, 0, 9, 4, 2 are inserted in that order into an initially empty binary search tree. The binary search tree uses the usual ordering on natural numbers. What is the inorder traversal sequence of the resultant tree?
A data structure is required for storing a set of integers such that each of the following operations can be done in $O(\log n)$ time, where n is the number of elements in the set.
1. Deletion of the smallest element.
2. Insertion of an element if it is not already present in the set.
Which of the following data structures can be used for this purpose?
The following numbers are inserted into an empty binary search tree in the given order: 10, 1, 3, 5, 15, 12, 16. What is the height of the binary search tree (the height is the maximum distance of a leaf node from the root)?
Assume that the operators +, -, x are left associative and ^ is right associative. The order of precedence (from highest to lowest) is $\wedge, x, +, -$. The postfix expression corresponding to the infix expression $a+b\times c-d\wedge e\wedge f$ is
The infix expression $A+(B-C)^{*}D$ is correctly represented in prefix notation as
A one dimensional array A has indices 1.... 75. Each element is a string and takes up three memory words. The array is stored at location 1120 decimal. The starting address of A [49] is
The five items: A, B, C, D, and E are pushed in a stack, one after the other starting from A. The stack is popped four times and each element is inserted in a queue. Then two elements are deleted from the queue and pushed back on the stack. Now one item is popped from the stack. The popped item is
A full binary tree with n leaves contains
The expression $1^{*}2\wedge3^{*}4\wedge5^{*}6$ will be evaluated as
The feature in object-oriented programming that allows the same operation to be carried out differently, depending on the object, is
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stores in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively